1. Field of the Invention
The present invention relates to a pattern matching method, program and a semiconductor device manufacturing method and, is directed to position matching between an image of a semiconductor pattern and CAD data, for example.
2. Related Art
The accuracy of patterns in semiconductor lithography processes has been managed conventionally by measuring the dimensions of line patterns and the internal diameters of hole patterns in an image obtained with an SEM (Scanning Electron Microscope).
However, with the recent advances in miniaturization of LSIs (Large Scale Integrated Circuits), there is an increasing need of measuring a particular portion of patterns having complex geometries on the basis of tolerance data provided while LSIs are designed in addition to measuring the average dimensions of simple patterns. Accurate position matching between design data and an SEM image is a prerequisite for performing such measurement.
There has been one method for matching an SEM image to design data, in which an edge image is generated from CAD data, for example, and the SEM image, the edge image is smoothed with a smoothing filter, and then matching is performed based on the correlation between the images (Japanese Patent Laid-Open No. 2002-328015, for example).
However, the method disclosed in Japanese Patent Laid-Open No. 2002-328015 has a problem that when a high-magnification SEM image is obtained in order to evaluate changes in geometry, the difference between a geometry in the SEM image and a geometry in CAD data is large, which degrades the accuracy of matching.